Struction Cache of Titac2: a Case Study
نویسنده
چکیده
In this paper, we demonstrate the formal verification of a practical timed asynchronous circuit. The target circuit is obtained by abstracting the instruction cache subsystem of a real asynchronous processor, TITAC 2. We also show several techniques to improve our verification method. The improved verifier could verify the target circuit in approximately 15 minutes, using less than 20 MBytes of memory.
منابع مشابه
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تاریخ انتشار 1999